Analytical Modeling of Multithreaded Pipeline Performance

T h e throughput of pipelined processors suf fers due t o delays associated wi th ins t ruc t ion dependencies and m e m o r y latencies . Multithreaded architectures t r y t o tolerate such delays by sharing t h e pipeline wi th independent ins t ruc t ion threads. T h i s paper proposes a n analyt ic model which i s used t o quant i tate t h e advantage of multithreaded architectures. T h e analyt ic model provides a n exact solut ion, which is significantly better t h a n bounds obtainable f r o m s impler approzim a t e techniques. Unlike previous analyt ic models of such sys tems , t h e model presented here accepts a general dis tr ibut ion f o r t h e interlock delays wi th mult iple latencies . T h e model provides a m u c h quicker perform a n c e es t imate t h a n s imula t ion . T h e model has been validated f o r a var ie ty of input dis tr ibut ions using prev iously published simulation-based results.